To date, an operational transconductance amplifier (OTA) circuit is known as an amplifier capable of controlling transconductance (also referred to as “Gm”).
FIG. 1 is a diagram illustrating an example of the configuration of the related-art OTA circuit. An OTA circuit 10 includes three N-channel MOSFETs 11, 12, and 13, four current sources 14, 15, 16, and 17, two input terminals 18 and 19, two output terminals 20 and 21, and a control voltage input terminal 22.
In this regard, MOSFET is an abbreviation of metal-oxide-semiconductor field-effect transistor. Hereinafter an N-channel MOSFET is also referred to as an NMOS, and a P-channel MOSFET is also referred to as a PMOS.
The gate of the NMOS 11 is connected to the input terminal 18 applied with an input voltage Vin. The drain of the NMOS 11 is connected to the output terminal 20 from which an output current IoutX is output, and connected to a power source terminal via the current source 14. The source of the NMOS 11 is connected to the source of the NMOS 13 and is grounded via the current source 16.
The gate of the NMOS 12 is connected to the input terminal 19 applied with an input voltage VinX. The drain of the NMOS 12 is connected to the output terminal 21 from which an output current Iout is output, and is connected to the power source terminal via the current source 15. The source of the NMOS 12 is connected to the drain of the NMOS 13 and is grounded via the current source 17. The gate of the NMOS 13 is connected to the control voltage input terminal 22 externally applied with a control voltage Vc.
In the OTA circuit 10, it is possible to control Gm of the OTA circuit 10 by adjusting the magnitude of the control voltage Vc so as to change the resistance value of the NMOS 13.
However, in the configuration in FIG. 1, as a differential input voltage input between the gates of the NMOSs 11 and 12 becomes higher, the drain-to-source voltage of the NMOS 13 changes into a saturation area in which the NMOS 13 is unable to be used as a variable resistor. When the drain-to-source voltage of the NMOS 13 changes into the saturation area, distortions of the output currents output from the drains of the NMOSs 11 and 12 become large as illustrated in FIG. 2. Accordingly, the differential input voltage allowed to input into the OTA circuit is limited to a predetermined voltage range (for example, ±0.2 V).
The followings are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 10-303664,    [Document 2] Japanese Laid-open Patent Publication No. 2007-181032,    [Document 3] Japanese Laid-open Patent Publication No. 2008-283555, and    [Document 4] Japanese Laid-open Patent Publication No. 2003-152474.